Power reduction in CMOS platforms is essential for any application technology.\nThis is a direct result of both lateral scalingââ?¬â?smaller features at higher density, and\nvertical scalingââ?¬â?shallower junctions and thinner layers. For achieving this power\nreduction, solutions based on process-device and process-integration improvements, on\ncareful layout modification as well as on circuit design are in use. However, the drawbacks\nof these solutions, in terms of greater manufacturing complexity (and higher cost) and\nspeed degradation, call for ââ?¬Å?optimizedââ?¬Â solutions. This paper reviews the issues associated\nwith transistor scaling and related solutions for leakage and power reduction in terms of\ntopological design rules and layout optimization for digital and analog transistors. For\nstandard cells and SRAMs cells, leakage aware layout optimization techniques considering\ntransistor configuration, stressors, line-edge-roughness and more are presented. Finally,\ndifferent techniques for leakage and power reduction at the circuit level are discussed.
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